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IS25C128 IS25C256
128K-bit/ 256K-bit SPI SERIAL ELECTRICALLY ERASABLE PROM
ISSI
Advanced Information JULY 2006
(R)
FEATURES
* Serial Peripheral Interface (SPI) Compatible -- Supports SPI Modes 0 (0,0) and 3 (1,1) * Low power CMOS -- Active current less than 3.0 mA (2.5V) -- Standby current less than 20 A (2.5V) * Low-voltage Operation -- Vcc = 1.8V to 5.5V * Block Write Protection -- Protect 1/4, 1/2, or Entire Array * 64 byte page write mode -- Partial page writes allowed * 2.1 MHz Clock Rate (5V) * Self timed write cycles -- 5ms max @ 2.5V * High-reliability -- Endurance: 1,000,000 cycles per byte -- Data retention: 100 years * 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin PDIP packages available * Industrial and Automotive temperature ranges * Lead-free available
DESCRIPTION
The IS25C128 and IS25C256 are electrically erasable PROM devices that use the Serial Peripheral Interface (SPI) for communications. The IS25C128 is 128Kbit (16K x 8) and the IS25C256 is 256Kbit (32K x 8). The IS25C128/256 EEPROMs are offered in a wide operating voltage range of 1.8V to 5.5V for compatibility with most application voltages. ISSI designed the IS25C128/256 to be an efficient SPI EEPROM solution. The devices are packaged in 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin PDIP. The functional features of the IS25C128/256 allow them to be among the most advanced serial non-volatile memories available. Each device has a Chip-Select (CS) pin, and a 3-wire interface of Serial Data In (SI), Serial Data Out (SO), and Serial Clock (SCK). While the 3-wire interface of the IS25C128/256 provides for high-speed access, a HOLD pin allows the memories to ignore the interface in a suspended state; later the HOLD pin re-activates communication without reinitializing the serial sequence. A Status Register facilitates a flexible write protection mechanism, and a device-ready bit (RDY).
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
1
IS25C128 IS25C256
ISSI
(R)
PIN CONFIGURATION 8-Pin DIP and SOIC
CS SO WP GND
1 2 3 4
8 7 6 5
VCC HOLD SCK SI
PIN DESCRIPTIONS
CS SCK SI SO GND VCC WP HOLD Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Write Protect Suspends Serial Input
Chip Select (CS The CS pin activates the device. CS): CS Upon power-up, CS should follow Vcc. When the device is to be enabled for instruction input, the signal requires a High-to-Low transition. While CS is stable Low, the master and slave will communicate via SCK, SI, and SO signals. Upon completion of communication, CS must be driven High. At this moment, the slave device may start its internal write cycle. When CS is high, the device enters a power-saving standby mode, unless an internal write operation is underway. During this mode, the SO pin becomes high impedance. Write Protect (WP The purpose of this input signal is WP): WP to initiate Hardware Write Protection mode. This mode prevents the Block Protection bits and the WPEN bit in the Status Register from being altered. To cause Hardware Write Protection, WP must be Low at the same time WPEN is 1. WP may be hardwired to Vcc or GND. HOLD (HOLD This input signal is used to suspend the HOLD): HOLD device in the middle of a serial sequence and temporarily ignore further communication on the bus (SI, SO, SCK). Together with Chip Select, the HOLD signal allows multiple slaves to share the bus. The HOLD signal transitions must occur only when SCK is Low, and be held stable during SCK transitions. (See Figure 8 for Hold timing) To disable this feature, HOLD may be hardwired to Vcc.
PIN DESCRIPTIONS
Serial Clock (SCK): This timing signal provides synchronization between the microcontroller and IS25C128/ 256. Op-Codes, byte addresses, and data are latched on SI with a rising edge of the SCK. Data on SO is refreshed on the falling edge of SCK for SPI modes (0,0) and (1,1). Serial Data Input (SI): This is the input pin for all data that the IS25C128/256 is required to receive. Serial Data Output (SO): This is the output pin for all data transmitted from the IS25C128/256.
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
IS25C128 IS25C256
ISSI
(R)
SERIAL INTERFACE DESCRIPTION
MASTER: The device that provides a clock signal. SLAVE: The IS25C128/256 is a slave because the clock signal is an input. TRANSMITTER/RECEIVER: The IS25C128/256 has both data input (SI) and data output (SO). MSB: The most significant bit. It is always the first bit transmitted or received. OP-CODE: The first byte transmitted to the slave following CS transition to LOW. If the OP-CODE is a valid member of the IS25C128/256 instruction set (Table 3), then it is decoded appropriately. If the OP-CODE is not valid, and the SO pin remains in high impedance.
BLOCK DIAGRAM
VCC GND
STATUS REGISTER
16K x 8/32K x 8 MEMORY ARRAY
DATA REGISTER SI MODE DECODE LOGIC ADDRESS DECODER OUTPUT BUFFER
CS WP
SCK
CLOCK
SO
HOLD
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
3
IS25C128 IS25C256
ISSI
(R)
STATUS REGISTER
The status register contains 8-bits for write protection control and write status. (See Table 1). It is the only region of memory other than the main array that is accessible by the user. Block Protect (BP1, BP0), Bits 2-3: Together, these bits represent one of four block protection configurations implemented for the memory array. (See Table 2 for details.) BP0 and BP1 are non-volatile cells similar to regular array cells, and factory programmed to 0. The block of memory defined by these bits is always protected, regardless of the setting of WPEN, WP , or WEN.
Table 1. Status Register Format
Bit 7 WPEN Bit 6 Bit 5 Bit 4 X X X Bit 3 Bit 2 Bit1 Bit 0 BP1 BP0 WEN RDY
Notes: 1. X = Don't care bit. 2. During internal write cycles, bits 0 to 7 are temporarily 1's.
Table 2. Block Protection
Status Register Bits
Level 0 1(1/4) 2(1/2) 3(All) BP1 0 0 1 1 BP0 0 1 0 1
The Status Register is Read-Only if either: a) Hardware Write Protection is enabled or b) WEN is set to 0. If neither is true, it can be modified by a valid instruction. RDY Ready (RDY Bit 0: When RDY = 1, it indicates that RDY), the device is busy with a write cycle. RDY = 0 indicates that the device is ready for an instruction. If RDY = 1, the only command that will be handled by the device is Read Status Register. Write Enable (WEN), Bit 1: This bit represents the status of device write protection. If WEN = 0, the Status Register and the entire array is protected from modification, regardless of the setting of WPEN, WP pin, or block protection. The only way to set WEN to 1 is via the Write Enable command (WREN). WEN is reset to 0 upon power-up.
Array Addresses Protected
IS25C128 None 3000h -3FFFh 2000h -3FFFh 0000h -3FFFh IS25C256 None 6000h -7FFFh 4000h -7FFFh 0000h -7FFFh
Don't Care, Bits 4-6: Each of these bits can receive either 0 or 1, but values will not be retained. When these bits are read from the register, they are always 0. Write Protect Enable (WPEN), Bit 7: This bit can be used in conjunction with WP pin to enable Hardware Write Protection, which causes the Status Register to be read-only. The memory array is not protected by this mode. Hardware Write Protection requires that WP = 0 and WPEN = 1; it is disabled otherwise. Note: WPEN cannot be changed from 1 to 0 if the WP pin is already set to Low. (See Table 4 for data protection relationship)
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
IS25C128 IS25C256
ISSI
(R)
DEVICE OPERATION The operations of the IS25C128/256 are controlled by a set of instructions that are clocked-in serially SI pin. (See
Table 3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition of the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to input an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of SK. All bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Lowto-High transition of SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no internal programming were underway.
Table 3. Instruction Set
Name
WREN WRDI RDSR WRSR READ WRITE
Op-code
0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010
Operation
Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Array Write Data to Array
Address
A15-A0 A15-A0
Data(SI)
D7-D0 D7-D0,...
Data (SO)
D7-D0,... D7-D0,... -
Notes: 1. X = Don't care bit. For consistency, it is best to use "0". 2. Some address bits are don't care. See Table 5. 3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the array or Status Register to be ignored.
WRITE ENABLE (WREN) When Vcc is initially applied, the device powers up with both status register and entire array in a write-disabled state. Upon completion of Write Disable (WRDI), Write Status Register (WRSR), or Write Data to Array (WRITE), the device resets the WEN bit in the Status Register to 0. Prior to any data modification, a WREN instruction is necessary to set WEN to 1. (See Figure 2 for timing). WRITE DISABLE (WRDI) The device can be completely protected from modification by resetting WEN to 0 through the WRDI instruction. (See Figure 3 for timing).
READ STATUS REGISTER (RDSR) The Read Status instruction tells the user the status of Write Protect Enable, the Block Protection setting (see Table 2), the Write Enable state, and the RDY status. RDSR is the only instruction accepted when a write cycle is underway. It is recommended that the status of Write Enable and RDY be checked, especially prior to an attempted modification of data. The 8 bits of the Status Register can be repeatedly output on SO after the initial Op-code. (See Figure 4 for timing).
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
5
IS25C128 IS25C256
ISSI
(R)
WRITE STATUS REGISTER (WRSR) This instruction lets the user choose a Block Protection setting, and set or reset the WPEN bit. The values of the other data bits incorporated into WRSR can be 0 or 1, and are not stored in the Status Register. WRSR will be ignored unless both the following are true: a) WEN = 1, due to a prior WREN instruction; and b) Hardware Write Protection is not enabled. (See Table 4 for details). Except for the RDY status, the values in the Status Register remain unchanged until the moment when the write cycle is complete and the register is updated. Note: WPEN can be changed from 1 to 0 only if WP is already set High. Once completed, WEN is reset for complete chip write protection. (See Figure 5 for timing). READ DATA (READ) This instruction begins with the op-code and the 16-bit address, and causes the selected data byte to be shifted out on SO. Following this first data byte, additional sequential bytes are output. If the data byte in the highest address is output, the address rolls-over to the lowest address in the array, and the output could loop indefinitely. At any time, a rising CS signal completes the operation. (See Figure 6 for timing).
WRITE DATA (WRITE) The WRITE instruction begins with the op-code, the 16bit address of the first byte to be modified, and the first data byte. Additional data bytes may be written sequentially to the array after the first byte. Each WRITE instruction can affect the contents of a 64 byte page, but no more. The page begins at address XXXXXXXX XX000000, and ends with XXXXXXXX XX111111. If the last byte of the page is input, the address rolls over to the beginning of the same page. More than 64 data bytes can be input during the same instruction, but upon a completed write cycle, a page would only contain the last 64 bytes. The region of the array defined within Block Protection cannot be modified as long as that block configuration is selected. The region of the array outside the Block Protection can only be modified if Write Enable (WEN) is set to 1. Therefore, it may be necessary that a WREN instruction occur prior to WRITE. Hardware Write Protection has no affect on the memory array. Once Write is completed, WEN is reset for complete chip write protection. (See Figure 7 for timing).
Table 5. Address Key
Name AN Don't Care Bits IS25C128 A13-A0 A15-A14 IS25C256 A14-A0 A15
Table 4. Write Protection
WPEN
0 0 1 1 X X
WP
X X 0 0 1 1
Hardware Write Protection
Not Enabled Not Enabled Enabled Enabled Not Enabled Not Enabled
WEN
0 1 0 1 0 1
Inside Block
Read-only Read-only Read-only Read-only Read-only Read-only
Outside Block
Read-only Unprotected Read-only Unprotected Read-only Unprotected
Status Register (WPEN, BP1, BP0)
Read-only Unprotected Read-only Read-only Read-only Unprotected
Note: X = Don't care bit.
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
IS25C128 IS25C256
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VS VP TBIAS TSTG IOUT Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value -0.5 to + 6.5 -0.5 to Vcc + 0.5 -55 to +125 -65 to +150 5 Unit V V C C mA
ISSI
(R)
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE (IS25C256-2 and IS25C128-2)
Range Industrial Ambient Temperature -40C to +85C VCC 1.8V to 5.5V
Note: 1. ISSI offers Industrial grade for Commercial applications (0oC to +70oC).
OPERATING RANGE (IS25C256-3 and IS25C128-3)
Range Automotive Ambient Temperature -40C to +125C VCC 2.5V to 5.5V
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
7
IS25C128 IS25C256
ISSI
Test Conditions VCC = 5V, IOL = 3 mA VCC = 2.5V, IOL = 1.5 mA VCC = 1.8V, IOL = 0.15 mA VCC = 5V, IOH = -3 mA VCC = 2.5V, IOH = -0.4mA VCC = 1.8V, IOH = -0.1mA Min. -- -- -- 0.8 X VCC 0.8 X VCC 0.8 X VCC 0.7X VCC -1.0 VIN = 0V TO VCC VOUT = 0V TO VCC, CS = VCC -3 -3 Max. 0.4 0.4 0.2 -- -- -- VCC + 1 0.3 X VCC 3 3 Unit V V V V V V V V A A
(R)
DC ELECTRICAL CHARACTERISTICS
TA = -40C to +85C for Industrial, TA = -40C to +125C for Automotive. Symbol Parameter VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VIH VIL ILI ILO Output LOW Voltage Output LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Output HIGH Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current
POWER SUPPLY CHARACTERISTICS
TA = -40C to +85C for Industrial. Symbol Parameter ICC1 ICC2 ICC3 ISB1 ISB2 ISB3 Vcc Operating Current Vcc Operating Current Vcc Operating Current Standby Current Standby Current Standby Current Test Conditions Read/Write at 2.1 MHz (Vcc = 5V) Read/Write at 2.1 MHz (Vcc = 2.5V) Read/Write at 500 KHz (Vcc = 1.8V) Vcc = 5.0V, VIN = VCC or GND CS = Vcc Vcc = 2.5V, VIN = VCC or GND CS = Vcc Vcc = 1.8V, VIN = VCC or GND CS = Vcc Min. -- -- -- -- -- -- Max. 5.0 3.0 2.0 25 20 15 Unit mA mA mA A A A
POWER SUPPLY CHARACTERISTICS
TA = -40C to +125C for Automotive. Symbol Parameter ICC1 ICC2 ISB1 ISB2 Vcc Operating Current Vcc Operating Current Standby Current Standby Current Test Conditions Read/Write at 2.1 MHz (Vcc = 5V) Read/Write at 2.1 MHz (Vcc = 2.5V) Vcc = 5.0V, VIN = VCC or GND CS = Vcc Vcc =2.5V, VIN = VCC or GND CS = Vcc Min. -- -- -- -- Max. 6.0 3.0 30 20 Unit mA mA A A
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
IS25C128 IS25C256
ISSI
1.8V Vcc < 2.5V Min Max 0 -- -- 800 800 200 200 200 40 50 100 100 0 0 0 -- -- -- 0.5 2 2 -- -- -- -- -- -- -- -- -- 150 -- 100 250 250 10 2.5V Vcc 5.5V Min Max 0 -- -- 200 200 100 90 90 20 30 50 50 0 0 0 -- -- -- 2.1 2 2 -- -- -- -- -- -- -- -- -- 60 -- 50 100 100 5 Units MHz s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
(R)
AC Characteristics
TA = -40C to +85C for Industrial. Symbol fSCK tRI tFI tWH tWL tCS tCSS tCSH tSU tH tHD tCD tV tHO tLZ tHZ tDIS tWC CL = 100pF Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Hold Setup Time Hold Hold Time Output Valid Output Hold Time Hold to Output Low Z Hold to Output High Z Output Disable Time Write Cycle Time
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
9
IS25C128 IS25C256
AC Characteristics
TA = -40C to +125C for Automotive. Symbol fSCK tRI tFI tWH tWL tCS tCSS tCSH tSU tH tHD tCD tV tHO tLZ tHZ tDIS tWC CL = 100pF Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Hold Setup Time Hold Hold Time Output Valid Output Hold Time Hold to Output Low Z Hold to Output High Z Output Disable Time Write Cycle Time 2.5V Vcc 5.5V Min Max 0 -- -- 200 200 100 90 90 20 30 50 50 0 0 0 -- -- -- 2.1 2 2 -- -- -- -- -- -- -- -- -- 60 -- 50 100 100 5
ISSI
Units MHz s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
(R)
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
IS25C128 IS25C256
ISSI
(R)
TIMING DIAGRAMS
Figure 1. Synchronous Data Timing
CS
VIH VIL tCSS tCSH tWH tSU tH tWL
tCS
SK
VIH VIL VIH VIL
DIN
VALID IN tV tHO tDIS
HIGH-Z
VOH DOUT VOL
HIGH-Z
Figure 2. WREN Timing
CS
SK
DIN
WREN OP-CODE HIGH-Z
DOUT
Figure 3. WRDI Timing
CS
SK
DIN
WRDI OP-CODE HIGH-Z
DOUT
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
11
IS25C128 IS25C256
ISSI
CS
(R)
Figure 4. RDSR Timing
SK Instruction DATA OUT 76543210
Din
Dout
Figure 5. WRSR Timing
CS
SK Instruction DATA IN 765
Din
4
3
2
1
0
Dout
Figure 6. READ Timing
CS
SK Instruction Din BYTE Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA OUT 76543210
Dout
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
IS25C128 IS25C256
ISSI
(R)
Figure 7. WRITE Timing
CS
SK Instruction Din BYTE Address DATA IN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Dout
Figure 8. HOLD Timing
CS tCD SCK tHD HOLD tHZ DOUT tLZ tHD tCD
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
13
IS25C128 IS25C256
ISSI
Package Small Outline (JEDEC STD) Small Outline (JEDEC STD), Lead-free 300-mil Plastic DIP 300-mil Plastic DIP, Lead-free Small Outline (EIAJ STD) Small Outline (EIAJ STD), Lead-free Small Outline (JEDEC STD) Small Outline (JEDEC STD), Lead-free 300-mil Plastic DIP 300-mil Plastic DIP, Lead-free Small Outline (EIAJ STD) Small Outline (EIAJ STD), Lead-free
(R)
ORDERING INFORMATION Industrial Range: -40C to +85C
Voltage Range 1.8V to 5.5V Part Number IS25C128-2GI IS25C128-2GLI IS25C128-2PI IS25C128-2PLI IS25C128-2WI IS25C128-2WLI IS25C256-2GI IS25C256-2GLI IS25C256-2PI IS25C256-2PLI IS25C256-2WI IS25C256-2WLI
1.8V to 5.5V
ORDERING INFORMATION Automotive Range: -40C to +125C
Voltage Range 2.5V to 5.5V Part Number IS25C128-3GA3 IS25C128-3GLA3 IS25C128-3PA3 IS25C128-3PLA3 IS25C128-3WA3 IS25C128-3WLA3 IS25C256-3GA3 IS25C256-3GLA3 IS25C256-3PA3 IS25C256-3PLA3 IS25C256-3WA3 IS25C256-3WLA3 Package Small Outline (JEDEC STD) Small Outline (JEDEC STD), Lead-free 300-mil Plastic DIP 300-mil Plastic DIP, Lead-free Small Outline (EIAJ STD) Small Outline (EIAJ STD), Lead-free Small Outline (JEDEC STD) Small Outline (JEDEC STD), Lead-free 300-mil Plastic DIP 300-mil Plastic DIP, Lead-free Small Outline (EIAJ STD) Small Outline (EIAJ STD), Lead-free
2.5V to 5.5V
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Integrated Silicon Solution, Inc. -- 1-800-379-4774
Advanced Information Rev. 00E 06/13/06
PACKAGING INFORMATION
300-mil Plastic DIP Package Code: N,P
ISSI
E1
(R)
N
1 D SEATING PLANE B1
S
S
A
E
L FOR 32-PIN ONLY A1 e B B2
C eA
MILLIMETERS Sym.
N0. Leads A A1 B B1 B2 C D E E1 eA e L S
INCHES Min. Max.
Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should
Min.
8
Max.
be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
3.68 0.38 0.36 1.14 0.81 0.20 9.12 7.62
6.20 8.13
4.57 -- 0.56 1.52 1.17 0.33
9.53 8.26
6.60 9.65 -- 0.762
0.145 0.015 0.014 0.045 0.032 0.008 0.359 0.300
0.244 0.320
0.180 -- 0.022 0.060 0.046 0.013
0.375 0.325
0.260 0.380 -- 0.030
2.54 BSC 3.18 0.64
0.100 BSC 0.125 0.025
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. D 02/14/03
PACKAGING INFORMATION
150-mil Plastic SOP Package Code: G, GR
ISSI
(R)
N
E
H
1 D
SEATING PLANE
A
A1 e B
L
C
Symbol Ref. Std. No. Leads A A1 B C D E H e L
150-mil Plastic SOP (G, GR) Min Max Min Max Inches mm 8 8 -- 0.068 -- 1.73 0.004 0.009 0.1 0.23 0.013 0.020 0.33 0.51 0.007 0.010 0.18 0.25 0.189 0.197 4.8 5 0.150 0.157 3.81 3.99 0.228 0.245 5.79 6.22 0.050 BSC 1.27 BSC 0.020 0.035 0.51 0.89
Notes: 1. Controlling dimension: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be
measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 10/03/01
2
PACKAGING INFORMATION
200-mil Plastic SOP Package Code: W
ISSI
(R)
N
E
H
1 D
SEATING PLANE
A
A1 e B
L
C
Notes: 1. Controlling dimension: mm, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.
200-mil Plastic SOP (W) Symbol Ref. Std. No. Leads A A1 B C D E H e L Min Max Min mm 8 -- 2.16 0.10 0.23 0.35 0.45 0.15 0.35 5.15 5.35 5.18 5.40 7.70 8.26 1.27 BSC 0.51 0.85 Max Inches 8 -- 0.085 0.004 0.009 0.014 0.018 0.006 0.014 0.203 0.211 0.204 0.213 0.303 0.325 0.050 BSC 0.020 0.033
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. A 10/20/05
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